One of the most important integrated circuits is the DRAM. A typical DRAM comprises a very large array of memory cells arranged in rows and columns, each of which is adapted to store a binary digit (bit) that can be controllably read in and out of the cell. To store the bit between write and read operations, each memory cell generally includes a capacitor in series with a switch, generally a MOS transistor. To provide a large array of memory cells in a single silicon chip, it is important to use memory cells that are use little silicon area and that can be closely packed. Since the switching transistor necessarily must be located in the silicon wafer, one form of memory cells achieve a space saving by forming the storage capacitor over the top surface, rather than in the interior, of the silicon chip. A capacitor so formed is usually described as a stacked capacitor since it is generally formed by a multilayer stack on the top surface of the silicon chip.
Because of the small size and high density of such capacitors on the top surface of the chip, the process for forming them is demanding. The present invention provide an improved process for forming such stacked capacitors.